1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing an electrostatic discharge protective circuit.
2. Description of the Related Art
Electrostatic discharge (ESD) is one of the major causes for an integrated circuit (IC) to be damaged in an IC fabrication process. This is especially true for fabrication of a deep sub-micron IC. In order to overcome the problems caused by static electricity, an ESD protective circuit is incorporated between an internal circuit and a pad.
Additionally, because the gate oxide layer become thinner as the integration of the semiconductor devices is increased, the breakdown voltage of the gate oxide layer approaches or is lower than that of the source/drain. Therefore, the protection provided by the ESD protective circuit becomes less effective. Moreover, the internal circuit design usually follows the minimum design rules, so the allowance spaces between the contact hole and the edge of the doped region and between the contact hole and the edge of the gate electrode are too small to resist the huge electrostatic-discharge transient current. Hence, the chips are easily damaged by the ESD when the integration is high.
Typically, a coupled diode or a coupled metal-oxide semiconductor (MOS) is used as the ESD protective circuit. Since the power consumption of the coupled diode or coupled metal-oxide semiconductor is very large, the ESD protective circuit cannot resist the relatively high stress of the ESD. When the breakdown voltage of the gate oxide layer is lowered to a breakdown voltage of a MOS junction due to the reduction of the thickness of the gate oxide layer, the protecting performance of the ESD protective circuit is very much degraded.
FIGS. 1A through 1D are schematic, cross-sectional views of the conventional process for manufacturing an ESD protective circuit.
As shown in FIG. 1A, a substrate 10 having an isolation region 12 is provided. The isolation region 12 is used to define a device region 14 and a protective circuit region 16 in the substrate 10. The device region 14 and the protective circuit region 16 respectively comprise MOS transistors 18 and 20. The MOS transistor 18 includes a gate oxide layer 22, a polysilicon layer 24, a spacer 26 and a source/drain region 28 with a lightly doped drain (LDD) region (the source/drain region 28 comprises an N.sup.+ doped region and an N.sup.- doped region). The MOS transistor 20 includes a gate oxide layer 30, a polysilicon layer 32, a spacer 34 and a source/drain region 36 with an LDD region (the source/drain region 36 comprises an N.sup.+ doped region and an N.sup.- doped region).
As shown in FIG. 1B, self-aligned silicide (salicide) layers 38, 39, 40 and 41 are respectively formed on the polysilicon layers 24 and 32 and on the source/drain region 28 and 36 by a (salicide) process.
As shown in FIG. 1C, a patterned photoresist 42 is respectively formed to cover the device region 14, the salicide layer 40 and a portion of the salicide layer 41 of the protective circuit region 16. The distance between portions of the patterned photoresist 42 above the salicide layers 40 and 41 is about 2 micrometers. A portion of the salicide layer 41 exposed by the patterned photoresist 42 is stripped away by dry etching until a portion of the source/drain region 36 is exposed.
As shown in FIG. 1D, the photoresist 42 is removed. A photoresist 44 is formed to cover the device region 14. The spacer 34 is removed by using the photoresist 44 as a mask. An ion implantation step is used to form a doped region with a relatively high dosage (e.g., using N.sup.+ ions) in a portion of the source/drain region 36 previously covered by the spacer 34. Therefore, the source/drain region 36 is converted into a source/drain region 36a. In the subsequent process the photoresist 44 is stripped away. Subsequent conventional techniques well known to those skilled in the art are performed to complete the semiconductor device.
Typically, the ESD protective circuit and the internal circuit are simultaneously formed. Since the structure of the conventional ESD protective circuit comprises an N-type doped region with a relatively high dosage, the junction resistance can be decreased to achieve a uniform power dissipation. However, the junction breakdown voltage cannot be reduced even though the structure of the conventional ESD protective circuit comprises an N-type doped region with relatively high dosage. Hence, the protective ability of the ESD protective circuit is poor when the gate oxide layer is thinner than 35 angstroms.